The present invention relates to a CMOS image sensor that is suited to a solid image pickup device for use in, for example, digital cameras and mobile equipment.
As well known, a CMOS image sensor features easy manufacturing using the CMOS technology that is frequently used for manufacturing semiconductor devices and low power consumption. Further, as peripheral circuit such as a signal processor, etc. can be formed on one chip jointly with a sensing portion, the CMOS image sensor can be manufactured in a small size. Accordingly, this sensor is now attracting attention as an alternate device to CCD that was so far used as an image input device.
A CMOS image sensor that is presently available will be explained below referring to FIG. 1 and FIG. 2. FIG. 1 is a block diagram showing an entire structure of the CMOS image sensor and FIG. 2 is a circuit diagram showing a pixel portion. In FIG. 1 and FIG. 2, a CMOS image sensor 1 contains plural photodiodes Pd providing a pixel 2 and pixel amplifiers 3 connected to plural photodiodes Pd, which are arranged in an almost two dimensional regular grid shape to form a pixel portion 4. On the periphery of the pixel portion 4, a timing generating circuit 5, a vertical line scanning circuit 6, a noise canceling circuit 7, a horizontal line scanning circuit 8 and a reader 10 that has an output amplifier 9 are arranged.
Further, the pixel portion 4 is composed of plural cells Ce11, Ce12, . . . Ce21, Ce22, . . . that are arranged in an almost two dimensional regular grid shape. Each cell Ceij is composed of one photodiode Pd and 3 transistors; that is, are set transistor Rs, a driver transistor Dr, and an address transistor Ad. These cells Ceij are connected to reset lines RsL1, RsL2, . . . address lines AdL1, AdL2, . . . , reset drain voltage lines Rd1, Rd2, . . . and signal output lines S1, S2, . . . , respectively.
The operation of the CMOS image sensor 1 thus arranged will be briefly explained. First, rays of light from an object (not illustrated) is focused on the pixel portion 4 through an optical lens system and an optical image is formed. The photodiodes Pd providing pixels 2 contained in the pixel portion 4 generate electric charge from the focused light through the photoelectric conversion. The generated charge is accumulated for a fixed period in a floating junction Fj that is a connecting portion between a photodiode Pd and a gate of each driver transistor Dr, generating an electric potential corresponding to the light quantity condensed in the pixels 2. The electric potential at the floating junctions Fj becomes a pixel signal.
The potential change in the floating junction Fj is applied to the gate of the driver transistor Dr so as to control the operating state of the driver transistor Dr. That is, reset drain voltage is applied to drain electrodes of the address transistors Ad through reset drain voltage lines Rd and address lines AdL are connected to gate electrodes of the address transistors Ad. When address voltage is ON, the address transistors Ad is placed in the ON state and reset train voltage is applied to the drain electrodes of the driver transistors Dr through this address transistors Ad. Therefore, the driver transistors Dr are put in the operating state and output the voltage corresponding to the electric potential of the gates of the driver transistors Dr to a signal output line S.
The vertical line scanning circuit 6 operates according to the signal from the timing generating circuit 5 and drives plural address lines AdL sequentially by the vertical line scanning circuit 6. In the columns selected through these address lines AdL, pixel signals having signal charge generated in the pixels 2 arranged side by side in the horizontal direction of the lines, for example, photodiodes Pd11, Pd12, . . . are generated in signal output lines S1, S2, . . . arranged in the horizontal direction. Then, the pixel signals are sent to the noise canceling circuit 7 through the signal output lines S1, S2, . . . wherein fixed pattern noises are removed and kept in the noise canceling circuit 7. Thereafter, the signals are time serially read out by the horizontal scanning circuit 8 and output as image signals after amplified by the output amplifier 9.
However, in a conventional CMOS image sensor described above, it is necessary to form two lines in the vertical direction: a signal output line S to output pixel signal and a reset drain voltage line Rd to apply reset drain voltage to the address transistor Ad for each cell Ce that is composed of a photodiode Pd, a reset transistor Rs, a driver transistor Dr and an address transistor Ad.
Similarly, it is also necessary to form two lines in the horizontal direction: a reset line RsL for resetting a floating junction Fj connected to a reset transistor Rs at drain voltage after reading pixel signals and an address line AdL for applying address pulse that is a signal from the vertical line scanning circuit 6 to the address transistor Ad.
By the way, this kind of image sensor is always demanded for a high degree of integration and the achievement of the high level of integration of the pixel portion 4 becomes an issue. For achieving a high level of resolution, it is generally demanded to make photodiodes Pd and transistor elements small in size or to make wires fine. However, there is a limitation on the high level of integration using such method as well as on the improvement of resolution of a conventional CMOS image sensor.
The present invention is made in view of the above-mentioned circumstances and it is an object to provide an CMOS image sensor that is capable of improving resolution in the horizontal direction as well as the vertical direction by efficiently arranging component elements and wires comprising pixel portions without making component elements and wires small or fine.
A CMOS image sensor according to an embodiment of the present invention has a first pixel group, in which a plurality of pixels composed of a combination of photoelectric conversion elements, reset transistors, driver transistors and address transistors are arranged in a matrix at a prescribed pitch in the horizontal and vertical directions, respectively. The CMOS image sensor further has a second pixel group, in which a plurality of pixels similarly composed of a combination of photoelectric conversion elements, reset transistors, driver transistors and address transistors are arranged in a matrix at a prescribed pitch in the horizontal and vertical directions, respectively, and are dislocated by about one-half of the prescribed pitch in the horizontal and vertical directions from the first pixel group. The CMOS image sensor further has reset lines belonging to the first and second pixel groups and are connected commonly to reset transistors arranged in the corresponding lines extending in the horizontal direction of the matrix arrangement, address lines similarly belonging to the first and second pixel groups and are connected commonly to the address transistors arranged in the corresponding lines extending in the horizontal direction of the matrix arrangement. The CMOS image sensor further has a plurality of first signal output lines belonging to the first pixel group and are connected commonly to the driver transistors arranged in the vertical direction of the matrix arrangement, and a plurality of second signal output lines similarly belonging to the second pixel group and are connected commonly to the driver transistors arranged in the vertical direction of the matrix arrangement.
Further, a CMOS image sensor according to another embodiment of the present invention has a first pixel group, in which a plurality of pixels composed of a combination of photoelectric conversion elements, reset transistors, driver transistors and address transistors are arranged in a matrix at a prescribed pitch in the horizontal and vertical directions, respectively. The CMOS image sensor further has a second pixel group, in which a plurality of pixels similarly composed of a combination of photoelectric conversion elements, reset transistors, driver transistors and address transistors are arranged in a matrix at a prescribed pitch in the horizontal and vertical. directions, respectively, and are dislocated by about one-half of the prescribed pitch in the horizontal and vertical directions from the first pixel group. The CMOS image sensor further contains an integrated circuit pattern, in which the photoelectric conversion elements belonging to the first pixel group and provided adjacent to each other in the horizontal direction and the photoelectric conversion elements belonging to the second pixel group and provided adjacent to each other in the vertical direction are arranged at four corners of a substantial square, a reset drain terminal is arranged at the center of the square.
Further, the driver transistor and the address transistor are arranged at two sides of the square, and the reset transistor and a floating junction that is a connecting portion of the reset transistor with the driver transistor are arranged on the remaining two sides of the square.